short information cdc 32xxg oct/2000 cdc 32xxg car dashboard controller (128-pin pqfp package) introduction v1.0 the cdc 32xxg is a microcontroller for use in automo- tive applications. the on-chip cpu is an arm pro- cessor arm7tdmi ? with 32 bit data and address bus, which supports thumb ? format instructions. the chip contains timer/counters, interrupt controller, multi channel a/d converter, stepper motor and lcd driver, can interfaces and pwm outputs and a crystal clock multiplying pll. table 1: cdc 32xxg family feature list item cdc 3205g-a1 cdc 3205g-b1 cdc3207g CDC32XXG core cpu 32 bit arm7tdmi ? cpu operation modes deep slow, slow, fast and pll cpu clock multiplication pll delivering up to 24 mhz pll delivering up to 24 mhz (20 mhz with erm) emi reduction mode - selectable in pll mode quartz oscillator 4 to 5 mhz ram, 32 bit wide 16 kbyte 24 kbyte 8 kbyte rom romless, flash port for connection of external program storage with up to 16 mbyte. internal boot rom. 512 kbyte flash eeprom, top boot configura- tion. internal boot rom. 256 kbyte rom digital watchdog 4 central clock divider 4 interrupt controller expand- ing irq 40 inputs,16 priority levels 32 inputs,16 pri- ority levels port interrupts including slope selection 6 inputs patch module - 10 rom locations 6 rom locations boot system allows in-system downloading of external code to flash memory via jtag -
cdc 32xxg short information 2 micronas oct/2000 analog reset/alarm combined input for regulator input supervision clock and supply supervi- sion 4 10 bit adc, charge balance type 16 channels (6 selectable as dig- ital input) 16 channels (each selectable as digital input) comparators p06comp with 1/2 avdd refer- ence p06comp with 1/2 avdd reference, waitcomp with internal bandgap reference adc reference pin pin or internal bandgap selectable lcd internal processing of all analog voltages for the lcd driver communication dma 1 dma channel for parallel load of an 8 bit port (fast load of an external lcd driver) or of a serial synchronous peripheral interface. uart 2 1 synchronous serial periph- eral interfaces 2 full can modules v2.0b 3 with 256 bytes of object ram (lcan0009) 3 with 512bytes of object ram 1 with 256 bytes of object ram, 1 with 512 bytes of object ram digitbus 1 master module i 2 c 2 master modules 1 master module input & output universal ports selectable as 4:1 mux lcd segment/back- plane lines or digital i/o ports up to 54 i/o or 50 lcd segment lines (=200 segments) up to 52 i/o or 48 lcd segment lines (=192 segments), individually configurable as i/o or lcd universal port slew rate mask selectable sw selectable stepper motor control mod- ules with high current ports 7 modules, 32 di/dt controlled ports pwm modules, each config- urable as two 8bit pwms or one 16 bit pwm 6 modules phase-frequency modulator - 1 audio module with auto- decay 4 sw selectable clock outputs 2 table 1: cdc 32xxg family feature list item cdc 3205g-a1 cdc 3205g-b1 cdc3207g CDC32XXG
short information cdc 32xxg micronas oct/2000 3 arm and thumb are the registered trademarks of arm limited. arm7tdmi ? is the trademark of arm limited. abbreviations am audio module can controller area network module capcom capture/compare module ccc capture/compare counter cpu central processing unit dma direct memory access module erm emi reduction mode etm embedded trace module icu interrupt controller i2c i 2 c interface module lcd liquid crystal display module p06comp p0.6 alarm comparator pint port interrupt module pwm 8bit pulse width modulator module sm stepper motor control module spi serial synchronous peripheral interface ttimer uart universal asynchronous receiver transmitter wcomp wait comparator timers & counters 16 bit free running counters with capture/compare mod- ules ccc0 with 4 capcom ccc1 with 2 capcom 16 bit timers 1 8bit timers 4 miscellaneous scalable layout in can, ram and rom - 4 various randomly selectable hw options most options sw programmable, copy from user program storage during system start-up mask pro- grammed accord- ing to user specification jtag test interface 4 allows flash pro- gramming 4 on chip debug aids embedded trace module, jtag jtag core bond-out 4 - supply voltage 4.5 to 5.5 v 3.5 to 5.5 v (pll mode when flash is internally supplied: 4.1 to 5.5 v) 3.5 to 5.5 v ambient temperature range - 40 to +85 c package type ceramic 257pga plastic 128qfp 0.5mm pitch bonded pins 256 128 table 1: cdc 32xxg family feature list item cdc 3205g-a1 cdc 3205g-b1 cdc3207g CDC32XXG
cdc 32xxg short information 4 micronas oct/2000 fig. 1: cdc 3205g-1 block diagram arm7tdmi cpu romless or 512k flash can 0 can 1 can 2 10bit adc uart 0 audio module pll watchdog clock 40 input interrupt controller stepper motor control lcd control uart 1 uport1 uport2 uport7 hport0 hport1 hport2 hport3 16bit ccc 0 pport1 spi 0 clock out 0 clock out 1 dma logic 4 6 8 8 7 8 4 4 5 6 6 6 xtal1 xtal2 test resetq vref avdd avss hvdd3 hvss3 hvdd0 hvss0 reset/alarm te s t data-, address- and control bus, (emu only) evdd evss spi 1 boot rom digitbus jtag test and debug interface 5 etm (emu only) bridge bridge p06 comp. i 2 c 0 i 2 c 1 capcom 0 capcom 1 capcom 2 16bit ccc 1 capcom 3 capcom 4 capcom 5 8bit timer 4 8bit timer 3 8bit timer 2 8bit timer 1 16bit timer 0 8bit pwm 0 8/16b pwm 1 pport0 8 hport4 4 uport6 uport3 uport4 uport5 hvdd1 hvss1 hvdd2 hvss2 vdd vss test2 21 52 32 16 8 16k sram uvdd uvss hport7 4 uport0 8 uport8 6 8bit pwm 2 8/16b pwm 3 8bit pwm 4 8/16b pwm 5 8bit pwm 6 8/16b pwm 7 8bit pwm 8 8/16b pwm 9 8bit pwm 10 8/16b pwm 11 memory controller
short information cdc 32xxg micronas oct/2000 5 fig. 2: cdc 3205g-2 block diagram arm7tdmi cpu romless or 512k flash can 0 can 1 can 2 10bit adc uart 0 audio module pll/erm watchdog clock 40 input interrupt controller stepper motor control lcd control uart 1 uport1 uport2 uport7 16bit ccc 0 spi 0 clock out 0 clock out 1 dma logic 4 4 8 8 7 8 4 4 3 4 4 4 xtal1 xtal2 test resetq vref avdd avss hvdd3 hvss3 hvdd0 hvss0 reset/alarm te s t data-, address- and control bus, (emu only) evdd evss spi 1 patch module boot rom digitbus jtag test and debug interface 5 etm (emu only) bridge bridge bandgap ref. p06 comp. wait comp. i 2 c 0 i 2 c 1 capcom 0 capcom 1 capcom 2 16bit ccc 1 capcom 3 capcom 4 capcom 5 8bit timer 4 8bit timer 3 8bit timer 2 8bit timer 1 16bit timer 0 8bit pwm 0 8/16b pwm 1 8 4 uport6 uport3 uport4 uport5 hvdd1 hvss1 hvdd2 hvss2 wait waith test2 21 52 32 16 8 24k sram uvdd uvss phase-freq.- modulator 4 uport0 8 uport8 6 8bit pwm 2 8/16b pwm 3 8bit pwm 4 8/16b pwm 5 8bit pwm 6 8/16b pwm 7 8bit pwm 8 8/16b pwm 9 8bit pwm 10 8/16b pwm 11 3.3v reg. 2.5v reg. fvdd uvdd vdd fvss uvss vss bvdd 2.5v reg. hport0 hport1 hport2 hport3 hport4 hport5 hport6 hport7 4 4 pport0 pport1 pport2 2 memory controller vrefint
cdc 32xxg short information 6 micronas oct/2000 all information and data contained in this short information are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. product or development sample availability and delivery are exclusively subject to our respective order confirmation form. by this publication, micronas gmbh does not assume responsibility for patent infringements or other rights of third parties which may result from its use. micronas gmbhs prior written consent must be obtained for reprinting. edition oct.13, 2000 order no. 6251-540-1si micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com
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